1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of stacked wiring layers, i.e., multilayer interconnection layers, and the present invention also relates to a manufacturing method of the semiconductor device which is suitable for forming an insulating layer to constitute the multilayer interconnection layers.
2. Description of the Related Art
With an increase in integration of ultra high semiconductor integrated circuit (hereinafter referred to as an LSI), discrete elements to be formed with a dimensional accuracy less than 1/4 .mu.m has been nowadays formed near a silicon substrate.
The LSIs exhibit no functions as a system until fine discrete elements are electrically coupled therebetween with wirings.
When the wrings to couple the individual discrete elements detour in order to avoid crossing of them, however, an area in chips occupied by the wirings increases and a wiring length increases, resulting in a wiring delay. Therefore, in order to prevent crossing points of the wirings and overlapping of them, technologies to couple the discrete elements with wirings having multi-wiring structure have been popularly employed. The multi-wiring structure is realized by arranging an insulating film between the wirings.
FIG. 3 shows a conceptional view of a multilayer interconnection. Referring to FIG. 3, an insulating film 31 is formed on a silicon substrate 1. A contact hole 4 is formed to make a connection to an element formation region 2. A contact plug 4 is formed to bury the contact hole 4, whereby the connection of the element formation region 2 to a first wiring layer 51 is achieved.
Moreover, the connection of the first wiring layer 51 to a second wiring layer 52 is made through a via plug 61 buried in a via hole 61 opened in the insulating film 32. The connection of the second wiring layer 52 to a third wiring layer 53 is made via a via plug 62 buried in a via hole 62 again opened in an insulating film 33. By repeating the above-described process, it will be possible to obtain a multilayer interconnection composed of more stacked layers. Formation of the multilayer interconnection is completed when a finally formed wiring is covered with a sealing film 7.
However, in the technology for the multilayer interconnection in which a thin insulating film is interposed between wiring layers, a large quantity of a floating capacitance between the wirings causes a wiring delay, and cross talk occurs when a signal containing high frequency components through the two wirings holding an interlayer insulating film therebetween is transmitted, resulting in occurrence of erroneous operations.
In order to prevent such wiring delay and cross talk, an increase in a distance between upper and lower wirings holding the interlayer insulating film is required, that is, a thickness of the interlayer insulating film must be set large. On the other hand, when the thickness of the interlayer insulating film is set large, a contact hole and via hole must be formed deeply. The formation of the deep contact hole and via hole makes a dry etching technique to form these holes more difficult. From this viewpoint, it is necessary to make the thickness of the interlayer insulating film thin as possible.
Hereafter, in a semiconductor integrated circuit technology to be put to a practical use after 256 megabits DRAM (dynamic random access memory), a diameter of a contact hole must be less than 1/4 .mu.m. From the viewpoint of a dry etching technique, when it is intended to make an aspect ratio, i.e., a ratio of a depth of the contact hole to a diameter thereof, at most less than 5, the thickness of the interlayer insulating film must necessarily be less than about 1 .mu.m.
Moreover, in addition to the above-described problems of the upper and lower wiring layers interposing the interlayer insulating film, problems of wiring delay and cross talk due to an increase in a floating capacitance between wirings formed on the same surface are severer as the integration grade of the semiconductor integrated circuit increase.
The reason of this is as follows. With micronization of the semiconductor integrated circuit, an interval between the wirings reduces as well as a width of the wiring, so that the width thereof becomes necessarily equal to 1/4 .mu.m. However, it is not allowed to make the interval of the wirings larger because of the requirement for the high integration of the semiconductor integrated circuit. Therefore, the problems of the wiring delay and cross talk between the wirings disposed in the same surface level are severer than those between the upper and lower wirings interposing the interlayer insulating film, which are solved by making the thickness of the inter-layer insulating film larger.
In order to obtain the wiring delay and cross talk accurately due to the increase in the wiring capacitance, the increase in the wiring capacitance being related to the thickness of the interlayer insulating film as to the upper and lower wirings or related to the integration degree of the semiconductor integrated circuit including the wirings formed on the same surface level, it is necessary to approach the wiring delay and cross talk with means like a distributed constant circuit.
This approach to the wiring delay and cross talk will be described with reference to FIG. 1. FIG. 1 shows a capacitance per unit wiring length between a silicon substrate wiring and a wiring layer insulated by an oxide silicon film of a thickness H (specific dielectric constant: 3.9), disclosed by L. M. Dang et al., IEEE, Electron Device Letters, No. EDL-Vol. 2, p. 196, 1981.
In the above paper, it is disclosed that a capacitance C increases remarkably compared to a capacitance similar to a so called parallel plate, by a fringe effect as the wiring width W reduces. At the same time, the presence of the fringe effect shows the fact that the more increase in the capacitance C is brought about compared to the capacitance similar to the parallel plate when a wiring height H is large.
It seems that an insulating film disposed between a silicon substrate and a lowermost wiring as shown in FIG. 1 is never called an interlayer insulating film. However, the problems of the wiring delay and cross talk are common to this insulating film, and, in the description of the specification for this application of the present invention, the insulating film which is formed directly on the silicon substrate to insulating electrically the wirings shall be also called an interlayer insulating film.
Furthermore, changes of the capacitance Cf per unit length between the wiring and the silicon substrate with advancement of micronization of the interval of the wirings are shown FIG. 2 which is described in the above dissertation. Although a capacitance C11 between the wiring and the silicon substrate reduces with the advancement of the micronization of the interval S of the wirings, a capacitance C12 between the wirings which are adjacent to each other separated by said interval S increases. As a result, when W/H exceeds 1, the capacitance Cf per unit length between the silicon substrate and the wiring increases as the micronization advances.
Specifically, although an operation speed of the elements constituting the semiconductor integrated circuit can be increased by micronizing the elements, when the wirings connecting the elements are micronized, an operation speed of the whole of the semiconductor integrated circuit will never increase because of the increase in the floating capacitance as well as an increase in a wiring resistance.
The results shown in FIGS. 1 and 2 are given by analyzing the floating capacitance between the silicon substrate and the wiring disposed interposing the insulating film. They are not result concerning the floating capacitance between the wirings. However, the qualitatively equal results can be obtained concerning the floating capacitance between the wiring layers. Therefore, in the description in the specification of this application, the films including an insulating film which is inserted between the silicon substrate and the lowermost wiring layer to electrically insulate them shall be called an interlayer insulating film.
To cope with such technical background, development of an interlayer insulating film of small specific dielectric constant.epsilon..sub.r must be hastened, instead of Si.sub.3 N.sub.4 of specific dielectric constant.epsilon.r-7 and SiO.sub.2 of specific dielectric constants.epsilon.-3.9, which are insulating films popularly used in the semiconductor integrated circuit technology. For substances of small specific dielectric constant, amorphous carbon fluoride films containing carbon and fluorine as main components, which achieves a specific dielectric constant.epsilon. less than 3, has been expected. This amorphous carbon fluoride is disclosed in Japanese Patent Laid Open No. Heisei 08-83842 (Prior Art No. 3), No. Heisei 08-222557(Prior Art No. 4), and No. Heisei 08-236517 (No. Prior Art No. 5). These amorphous carbon fluoride films are formed in such manner that first hydrocarbon type gas and fluorine type gas are changed to plasma gas or CxFy gas is changed to plasma gas, and radical molecules or ions of generated carbon and fluorine react on the silicon substrate to form the amorphous carbon fluoride film. Some amorphous carbon fluoride films contain nitrogen atoms or silicon atoms in order to enhance heat resistance property and etching resistance property.
Since the foregoing amorphous carbon fluoride film has a low specific dielectric constant.epsilon.r, it is expected much as an interlayer insulating film in the multilayer wiring structure. However, the amorphous carbon fluoride film involves technical problems on the formations of a contact hole to connect the wiring to a semiconductor diffusion layer and a via hole to connect between the wirings. Consequently, putting to practical use of the amorphous carbon fluoride film is obstructed.
Processes to form an opening in the amorphous carbon fluoride film will be described with reference to Japanese Patent Laid Open No. Heisei 5-74962 (Prior Art 2), which discloses a technology to form a through hole in an interlayer insulating film formed of SiO.sub.2 using an ordinary photolithography technique.
An ordinary resist formed by combining phenol resin and photosensitive material or by combining photosensitive material and resin such as cyclorubber is coated on the amorphous carbon fluoride film to a thickness of 1 to 1.5 .mu.m, and a hole of a diameter 0.2 .mu.m is perforated in the amorphous carbon fluoride film, on the supposition of processes for fabricating large scale semiconductor integrated circuit more than 64 megabits DRAM (Dynamic random access memory).
These processes realize the structure as is shown in FIG. 3. Technology to form a contact hole 4 or a via hole 61 or 62, in an amorphous carbon fluoride film 31, 32 or 33 as an interlayer insulating film, will be described.
First, the foregoing ordinary resist film is coated on the amorphous carbon fluoride film. Thereafter, the resist film is subjected to exposure and developing sequentially, thereby forming a selection mask for selective etching. Subsequently, a hole is formed in the amorphous carbon fluoride film using this resist film as a mask by means of an ion milling method.
This ion milling method for opening the hole was employed because the amorphous carbon fluoride film exhibits a strong resistance to acid and alkali so that it can not be etched. However, since perforating of the hole in the amorphous carbon fluoride film is conducted using the ion milling method which is substantially pure physical process, the resist film as the mask itself is etched at the stage of perforation of the hole in the amorphous carbon fluoride film. For this reason, when the resist film of a thickness more than 1 .mu.m was formed, the opening could be hardly formed for the amorphous carbon fluoride film of a thickness less than 0.4 .mu.m. However, the perforation of the opening for the amorphous carbon fluoride film of the thickness more than 0.4 .mu.m was extremely difficult.
Moreover, the resist film must be removed after the perforation of the opening by means of the ion milling method. It was found that a reduction in the thickness of the amorphous carbon fluoride film occurs by a wet processing using a resist removing liquid heated to about 100.degree. C.
The resist removing was tried by means of ashing processing in oxygen plasma. However, it was found that the amorphous carbon fluoride film was rapidly removed together with the resist film also by means of ashing processing. Specifically, working for the amorphous carbon fluoride film by ordinary photolithography techniques is extremely difficult.